VOVHDL: A verification-oriented dialect of VHDL*

The boundaries of hardware description are rapidly migrating towards higher and higher levels of abstraction. Until not long ago, designers mainly worked at register-transfer level, whereas new activities at system-level are now emerging. Systems are conceived before partitioning between hardware and software realization takes place, so that many alternatives can be explored before defining the final hardware/software architecture. Among the most relevant activities at system-level, we list specification description and validation, and system description and verification. Most efforts in the past concentrated on hardware description, whereas validation and verification were mainly based on simulation. This research activity aims at a complete design methodology that is able to guarantee system verifiability at each design step, from the initial specification down to the final implementation, using a set of automated tools. Verifiability is not free of charge: restrictions, that assume the form of Design for Verifiability rules [Miln89b], [CaPr91], must be imposed both on the design methodology and on the description formalism, as what happened in the field of testing with Design for Testability [WiPa82].